1. Field of the Invention
The invention relates to decoder circuits, and more particularly to MOSFET decoder circuits for semiconductor random access memory devices.
2. Description of the Prior Art
Integrated circuit semiconductor random access memories have been implemented utilizing MOSFETs (also commonly called IGFETs). Such random access memories (RAMs) typically include a relatively large array of storage cells and decoding circuitry which selects one row and one column so that the particular storage cell located at the intersection of the selected row and selected column is accessed so that its contents can be modified during a write cycle or its contents can be sensed during a read cycle. To accomplish this type of row and column selection, row and column decoders are utilized. Such decoders are typically implemented utilizing dynamic NOR gates each having an IGFET which initially precharges the output of the respective NOR gate. Address input buffers then provide signals to the inputs of the NOR gates which are decoded by the NOR gates. The address buffer outputs are connected to the NOR gate inputs so that each unique combination of binary address inputs selects one and only one decode gate. None of the switching IGFETs for the selected row decode gate and column decode gate are turned on, but at one or more switching IGFETs for all of the unselected code gates are turned on. Column selection circuitry or row selection circuitry is connected to the output of each NOR gate. The output, of the column or row selection circuitry are called column select lines and row select lines and are coupled to each of the cells in the respective rows or columns. Since only one row and one column can be selected during a particular memory cycle, it is imperative that all unselected select lines be maintained at a logical "0". This is frequently accomplished by utilizing discharge circuitry coupled to each select line for both rows and columns, which discharge circuitry discharges all select lines to ground voltage at the same time that the NOR gate load MOSFETs precharge all of the NOR gate outputs to a positive voltage in an N-channel memory circuit. However, this approach suffers from the disadvantage that such discharge circuitry typically requires additional power dissipation and chip area.